1. Field
The present specification describes a level shift circuit, and more particularly a level shift circuit which is capable of preventing occurrence of malfunctions when a low power voltage supply fluctuates. The present specification further describes a semiconductor integrated circuit which includes the above-mentioned level shift circuit.
2. Discussion of the Background
FIG. 1 shows a conventional level shift circuit 101 and FIG. 2 shows its exemplary operation. As shown in FIG. 1, the level shift circuit 101 includes P-channel MOS (metal oxide semiconductor) transistors (hereinafter referred to as PMOS transistors) 111 and 113 and N-channel MOS transistors (hereinafter referred to as NMOS transistors) 112 and 114. The PMOS transistors 111 and 113 and the NMOS transistors 112 and 114 are pulled up to a predetermined low power voltage Vdd1. These transistors are designed to be used with a relatively low withstand voltage. The level shift circuit 101 further includes PMOS transistors 115 and 117 and NMOS transistors 116 and 118. The PMOS transistors 115 and 117 and the NMOS transistors 116 and 118 are pulled up to a predetermined high power voltage Vdd2. These PMOS transistors 115 and 117 and the NMOS transistors 116 and 118 are designed to have a relatively high withstand voltage and therefore have a threshold voltage greater than that of the PMOS transistors 111 and 113 and the NMOS transistors 112 and 114.
As shown in the operation of FIG. 2, when a signal Si at low level is input through an input terminal IN of the level shift circuit 101, a signal S1 at high level substantially equivalent to the predetermined low power voltage Vdd1 is input through a gate of the NMOS transistor 118 and a signal S2 at low level, that is, 0 volts, is input through a gate of the NMOS transistor 116. Alternately, when the signal Si at high level is input through the input terminal IN, the signal S1 at low level, that is, 0 volts, is input through the gate of the NMOS transistor 118 and the signal S2 at high level substantially equivalent to the predetermined low power voltage Vdd1 is input through the gate of the NMOS transistor 116.
Thus, the high level signal of the predetermined low power voltage Vdd1 is input through the gates of the NMOS transistors 116 and 118 which are pulled up to the predetermined high power voltage Vdd2. The voltage of the high level signal input through the gates of the NMOS transistors 116 and 118 are greater than threshold voltages VthB and VthA of the NMOS transistors 116 and 118. As a result, the NMOS transistors 116 and 118 can be switched to an ON state without fail, and signals level-shifted from the input signal Si are output through output terminals OUT and OUTB.
However, when the level of the predetermined low power voltage Vdd1 is reduced due to an influence of electrical noise or the like, the input signals at high level input to the gates of the NMOS transistors 116 and 118 become likely lower than the threshold voltages VthB and VthA of the NMOS transistors 116 and 118, as shown in FIG. 3. In this case, the NMOS transistors 116 and 118 cannot be switched to an ON state and, as a consequence, the level shift circuit 101 cannot properly perform its operation.